Implementation of Digital Down Conversion Technique Using FPGA for Atmospheric RADAR Application

This paper discusses the design and implementation of FPGA-based Digital Down Converter (DDC) for RADAR signal processing applications. The features connected to DDCs have migrated over the past several years from ASIC implementations to IP cores in FPGA, which offer architectural flexibility, adjustable frequency and phase characteristics, greater precision computing, larger channel density, and low power and cost per channel. These advantages increase with the introduction of each new FPGA generation with increased performance. Any returned echo signal from the targets must be preprocessed before applying different signal processing algorithms for target detection. DDC helps in front-end processing of received echo signal. Results are analyzed using Xilinx ISE 12.4, Chip Scope Pro Analyzer, and MATLAB Simulation.