Drain Current and Transconductance Analysis of Double-Gate Vertical Doped Layer TFET

Due to its sharp subthreshold swing and low leakage current, VDL-TFET has become a potential option for low-power electronic devices. In this study, we examine the influence of various device settings on the electrical properties of VDL-TFETs to assess their performance in low-power applications. We analysis how the doping level, layer thickness, gate length, and temperatures affect the functionality of VDL-TFETs. Simulations conducted by us demonstrate that by carefully tuning those parameters, the device’s ON-current, subthreshold swing, and delay properties may be greatly enhanced, rendering it appropriate for low-power digital and analogue electronics. We additionally contrast the efficiency of VDL-TFETs against that of various other low-power transistors, including FinFETs, and show that the subthreshold swing and delay features of VDL-TFETs are comparable to those of FinFETs. According to our research, VDL-TFETs are an intriguing technology for low-power semiconductor purposes.