Multi-feature Data Generation for Design Technology Co-Optimization: A Study on WAT and CP

This study explores the use of Generative Adversarial Networks (GANs) to generate wafer-level Wafer Acceptance Test (WAT) and Chip Probe (CP) test data in semiconductor manufacturing processes, and their application in relevant process and Design-Technology Co-Optimization (DTCO). The generated virtual silicon data includes device performance, physical-electrical characteristics, distribution of wafer process parameters, and implicit information on wafer-level features such as uniformity and defects. This approach enables interdisciplinary teams to overcome data acquisition barriers while ensuring data confidentiality, and it holds significant potential for the development of advanced Electronic Design Automation (EDA) tools in co-optimizing process and chip design flows.