Implementation and Performance Optimization of JPEG Decoding Algorithm in Multi CPU Embedded System

As an efficient still image data compression algorithm, JPEG compression algorithm is widely used in many embedded multimedia products. The speed of image data encoding and decoding has become the most important aspect that restricts the improvement of product performance. In a single CPU embedded environment, JPEG encoding and decoding speed has almost reached the limit, and it is difficult to improve the space. However, the emergence of the multi-core embedded system represented by Fujitsu FR1000 in recent two years has made it possible to significantly improve the performance of multimedia products. In this paper, we JPEG decoding. The proposed and idea of selective optimization. It uses partial redundancy elimination (PREL) to avoid some redundant blocks in the JPEG decoder, and selects appropriate blocks for further processing according to the current image data. The whole process can be summarized as follows: 1) Initialize PREL; 2) Read all pixel values from the input buffer; 3) Selecting one or more blocks according to their contents for further processing; 4) Perform PREL on the selected block; 5) Process the remaining blocks to get the final result.