FPGA Implementation of Ternary Multiplier Using Reconfigurable Logic

The multiplier circuit of the ALU is one of the most crucial parts of the computer. Therefore, a powerful computer might be built by optimising the multiplication circuit. The suggested concepts in nanoscale integrated circuits aim to reduce power consumption and boost battery life. The current binary scheme and MOSFET technology used in two-level logic have some drawbacks. Three-level ternary logic technology is created to go around these restrictions. The proposed framework reconstructs the existing ternary multiplier in such a way that it needs to be applied for the various applications of trits multiplication. The multivalued logic system provides the more advantages compared with the binary logic in terms of the power consumption, area, and complexity of circuits (Sharma and Kumre in Circ Syst Sig Process 39(7):3265–3288, 2020 [1]). The data can be represented exponentially larger if MVL is employed to represent the data instead of binary logic with the same number of logic bits. In the future days the MVL based on the ternary logic can be applied for the ‘n’ number of applications due to its simple design and the different levels, i.e. zero and one can be easily distinguishable. Ternary logic has emerged as a viable alternative to binary logic in the design of high performance, energy-efficient VLSI circuits due to its reduced impact on interconnects, and chip size. In this work, we introduce the multivalued logic FPGA implementation of a multiternary digit (trit) multiplier.