Design of Energy-Efficient High-Speed 1-Bit Hybrid Full Adder for Fast Computation

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR–XNOR circuit. In this article, a high-speed, low-power 8-T XOR–XNOR circuit is proposed, which provides full-swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 45-nm CMOS technology with a supply voltage of 1.0 V. The power delay product (PDP) is reduced by proposed circuit.