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SVPWM Strategies to Reduce Common-Mode Voltage for Five-Level ANPC Inverter

  • Dinh-Long Tran,
  • Nho Van Nguyen

摘要

In this paper, a novel space vector pulse width modulation (SVPWM) is proposed to reduce common-mode voltage (CMV) of the three-phase five-level active neutral-point clamped (5L-ANPC), by utilizing only 55 selected voltage vectors among 125 voltage vectors to produce low values of the CMVs with the maximum modulation index (MI). A novel method to detect reference voltage vector and calculate its dwelling time is proposed. Besides, the flying capacitor (FC) voltages are controlled by the redundant switches of the 5L-ANPC inverters, making it balanced. This balancing method is derived by using the instantaneous measurements of output current and FC’s voltages. The simulation results showed that the peak of the CMV is decreased significantly to one twelfth of the DC link voltage, decrease in total harmonic distortion (THD) of the output voltages with out increasing the switching losses.