Design of Voltage Comparator with High Voltage to Time Gain for ADC Applications

In this paper, a two-stage comparator with high voltage to time gain, low input-referred noise, offset with lesser delay is introduced. The effect of noise can be greatly reduced by increasing the gain of the comparator and reducing load at input MOS pair. The addition of NMOS as input from the first stage output reduces the load at the input pair and clock-enabled NMOS breaks the supply to ground path when the clock is disabled with clock-enabled PMOS for the reset phase increasing the transconductance of the second stage. For fair comparison, conventional and proposed comparators are designed in 90-nm CMOS technology with 1.2 V supply voltage. Simulated results show that the proposed comparator has an input-referred noise of 71.2 \({\upmu \text {V}/\sqrt{\text {Hz}}}\) with input-referred offset of 7.299 \(\text {mV}\) at \({V}_{cm}\) of 600 mV with a delay of 91 \(\text {pS}\) and gain of 94.63 \(\text {V}^2/\text {s}\) at 1 GHz clock frequency. The output is 30% faster than conventional comparators, this improvement suits the criteria for high-precision ADCs as the noise and offset are low at the designed frequency across all the corners.