Efficient VLSI Architectures of Multimode 2D FIR Filter Bank using Distributed Arithmetic Methodology

For the implementation of the hardware structure of filter architecture, the area, power, and delay efficiency are needed. Memory complexity is also important in the 2D FIR filter architecture, while used for image processing applications. In this work, a memory-efficient 2D FIR filter bank architecture is designed using parallel processing, symmetry, and distributed arithmetic methodology. The symmetry concept decreases the quantity of the multipliers of the filter architecture. Parallel processing and multimode filter bank approaches will improve memory efficiency through memory reuse and memory sharing, respectively. The distributed arithmetic (DA)-based filter architectures reduce the multiplier complexity in terms of power and area. Four types of symmetry filter architectures along with one normal filter (without symmetry) are integrated as a multimode filter bank. The required filter can be selected by the control logic. In this filter bank, the memory module is shared by all the sub-filter, which is called memory sharing. The LUT-based DA methodology is used to implement the multipliers of each sub-filter arithmetic module. The proposed multimode filter bank architecture is implemented for the filter length N = 4 with two-level parallel processing using Xilinx Vivado tools. The utilization of resources is correlated with works mentioned in the literature. The area, timing delay and power consumption reports are generated using Genus synthesis tools in 45 nm CMOS technology from the Cadence vendor.