Low Power High Speed Modified GDI Full Adder Implemented by NCFET Technologies

This study introduces a novel full adder architecture that combines excellent performance with low power consumption. The proposed design utilizes the Gate Diffusion Input (GDI) and Modified Gate Diffusion Input (MGDI) approaches, which are known for their high speed and low power consumption properties. Additionally, Negative Capacitance Field Effect Transistor (NCFET) technology is used to implement the proposed full adders, which has been shown to improve digital circuit efficiency. The simulation results demonstrate that the proposed full adders significantly reduce power consumption and latency while maintaining a comparable area to existing designs. Overall comparison is made in terms of time delay, power consumption, and number of transistors used. The power consumption is approximately reduced to 90% and delay is approximately reduced to 40%, making an effective and efficient full adder logic design.