A Single Line 8T SRAM Bit Cell with Robust Read, Hold Stability and Low Power

This article is focussing on the analysis of an eight transistor SRAM bit cell which is accessed by single bit line. The various analyses, this brief includes, are power consumption, access time, delay and static noise margins of the 8TP cell with the preexisting single bit line 7T and 9T cells. After the analysis of these three cells, it is observed that amongst the three cells, the single bit line 8TP cell possess better performance in every aspect. All the three cells are evaluated on an operating voltage of 500 mV with the technology node 22 nm CMOS. The obtained values of SNM for hold of the 8TP cell is 256 mV, for read of the 8TP cell is 242 mV and for write of the 8TP cell is 311 mV. The value of dynamic power consumed by read operation of these cells is 26 µW for 7T cell, 31 µW for 9T cell and 22 µW for 8TP cell, while for write operation it is 4.6 µW for 7T cell, 2.8 µW for 9T cell and 2.8 µW for 8TP cell. The accessing time for read of 8TP cell is reduced by a multiple of 1.8 when compared with 7T cell and by a multiple of 1.3 when compared with 9T cell; similarly, accessing time for write of 8T cell is decreased by a multiple of 1.33 when compared with 7T cell and by a multiple of 1.77 when compared with 9T cell.