Design of Current Starved Voltage-Controlled Oscillator Using Gm/Id Methodology

The current starved voltage-controlled oscillator offers low power consumption, excellent integration capability and smaller area when compared to the other VCOs. A five-stage CSVCO for phase-locked loop (PLL) is designed using Gm/Id methodology. The tuning range is from 600 MHz to 1.3 GHz can be achieved by adjusting the control voltage of the VCO between 0.6 and 2 V. The supply voltage used is 1.8 V, and the circuit is designed using 180 nm CMOS technology. The circuit design and simulation of this work is carried out in Cadence Virtuoso EDA environment.