Hardware Implementation of Three-Layered Perceptron Using FPGA

Multi-Layered Perceptron Neural Networks (MLPNNs) are information processing systems, designed to function like a biological brain. These are a network of highly interconnected computational units called neurons which perform mathematical and operate in parallel. They have various applications in engineering, such as system modeling and control, pattern recognition, and medical diagnosis. These biologically-inspired network of computational units, perform parallel and distributed information processing and thus require high-speed operation capacity for real-world applications. This can be achieved by implementing MLPNNs on a Field Programmable Gate Array (FPGA). Application-specific, resource-efficient, and custom computational hardware blocks can be designed on it to perform the required computations, rather than the use of general-purpose computers, that use the same resources for all processes. This paper presents a method to implement MLPNNs on an FPGA with minimal FPGA resource utilization and maximum accuracy. The log sigmoid and tan sigmoid functions are used as activation functions to implement the MLPNN. MATLAB and Verilog Hardware Description Language (Verilog HDL) is used for software and hardware implementation and simulations. It is then implemented on Digilent’s ZYBO ZYNQ 7010 FPGA SoC Development Board. The comparison of MLPNNs implementing different activation functions are done based on their mean squared error (MSE), training time, testing time, the number of utilized look-up tables (LUTs), flip-flops, and DSPs on the FPGA.