Design and Implementation of Booth Multiplier with Sklansky and Ling Adders

Modern VLSI system design now places a high priority on power usage. Fast and space-efficient multipliers are required due to the rising need for quick floating-point coprocessors, digital signal processing devices, and graphics processors. The booth multiplier is one enhanced variation of a multiplier. It speeds up multiplication by using a unique technique known as the carry-save addition algorithm. The performance of the booth multiplier is being further improved by this research activity. This enhancement aims to reduce computation time as well as power consumption during multiplication. We offer a method that makes use of unique parts known as 4-2/5-2/7-2 compressors to accomplish this. Additionally, the Sklansky adder, a divide and conquer tree adder, is used. The results of this study project show that the novel strategy produces less processing time than the conventional approach. Additionally, it considerably reduces power consumption, particularly when the operation is carried out at 50 MHz. The Xilinx ISE tool, which is frequently employed for testing and assessing digital circuits, was used to conduct the simulations for this research project.