VLSI Floorplan Area Optimisation Technique

Floorplanning is a crucial phase in the physical design. It estimates the overall chip area, the interconnects, and the latency by determining the shape, size, and placements of the modules in a chip. The VLSI floorplan problem has been addressed by several researchers using a variety of heuristics and metaheuristic techniques. An essential component of the floorplan stage is the floorplan representation. The VLSI floorplanning problem is surveyed in this paper, along with a comparison of the various optimisation algorithms (like Simulated Annealing, Particle Swarm Optimisation, Differential Evolution, Ant Colony Optimisation as optimisation algorithms) and the representations involved in the VLSI floorplanning problem.