ASIC Design of High-Performance MIPS Processor Using Aprisa

In this present era of electronics, processors play a critical role. Everyone needs processors with low cost, high operating speed, and low power consumption. There are a wide range of unfavorable risks in processors as technology advances to sub-micrometer levels. These risks (hazards) could result in timing, area, and power disruptions that depart from the desired proportions. As technology shrinks, new architectures and better EDA tools are needed to implement them. Our paper primarily focuses on finding solutions to some of these problems with a tool named Aprisa. Here we propose a high-performance 32-bit pipelined MIPS processor which is designed and implemented using the tools from Siemens EDA, namely Oasys (synthesis tool) and Aprisa (place and route tool). The proposed architecture can also detect data hazards caused by pipelining. The entire ASIC flow is done using TSMC 45 nm libraries, and a frequency of 3.6 GHz is achieved with a power consumption of 18.4mWatts and an instance area of 9091 sq.m. Also, chip utilization of 85% is achieved with good routability. Also, the same work is done in the 16 nm lower node and both results are compared. Compared with existing work, the area got improved by 65% and the frequency got almost doubled.