A Comparative Performance Analysis of 10 T and 11 T SRAM Cells

Memory is already known to be one of the most crucial parts of any electronic system. However, a class of memory called the cache memory is even more crucial among the type of memories since it is the one working closely in synchronization with the central processing unit. There are millions of SRAM cells inside cache memory. SRAM cells must therefore possess a few essential attributes for cache memory to be reliable, including low dynamic and static power consumption, high data stability, and low read latency. To successfully incorporate these qualities, a comparative analysis of different 10 T and 11 T SRAM cells has been performed. The performance of the conventional TG10T and 11 T SRAM models is compared to the 10 T SRAM to showcase enhancements obtained. TG10T SRAM cell deploys two transmission gates instead of two NMOS access transistors to strengthen writing ability. It also employs two additional buffer transistors so that read stability can be enhanced. All simulations are carried out using LTSPICE software operating at 0.5 V in 32 nm CMOS process technology. The TG10T SRAM cell is proven to be more enhanced in almost every aspect, but it consumes more power. The read SNM and write SNM are found to be the largest in the TG10T SRAM cell. The power dissipated by the TG10T cell (i.e., 233.69 nW) is approximately two times as compared to the 10 T SRAM cell (i.e., 108.65 nW) and 11 T SRAM cell (i.e., 88.491 nW). The analysis also portrays that both read and write delay is minimum in TG10T SRAM cells. The read delay is 343.3 psec, and the write delay is 494 psec, respectively.