Low-Power High-Speed Modified Three-Stage Comparator with Low Kickback Noise

In this study, a three-level comparator architecture has been suggested to increase speed and decrease kickback noise. The additional amplified stage in the multiple comparators boosts voltage gain and speed in comparison to the traditional two-stage comparator. Furthermore, speed is increased by using nMOS input sets in both the regenerating and amplifies stages rather than just the regenerative stage as in the conventional two-stage arrangement. The three-stage comparator's kickback noise is greatly decreased by adding a pair of CMOS inputs at the amplification stage. This kickback noise is generated by NMOS kickback. Faster performance is achievable by introducing a second describing the steps while playback remains active. For better comparison, the suggested three-stage comparator and the standard two-stage comparator were both simulated by employing the identical 130-nm CMOS technology. According to the experimental findings, the redesigned comparator increases speed by 32% and decreases kickback noises by a factor of 10.