A Comprehensive Review to Investigate the Effect of Read Port Topology on the Performance of Different 7 T SRAM Cells

SRAM-based cache memory is an important component for microprocessor-based circuit. The growing demand for portable devices with prolonged battery life has driven designers to report SRAM bit cells with varying topologies. The 7T cell is one of the most popular bit cell topologies. As a consequence, five different 7T cells with a common internal memory core configuration and different read port topologies are reviewed in this paper. The technology node for each cell is 32 nm, while the supply voltage is 0.8 V. The cell topologies are analyzed for static noise margin and time requirement for each operation. It is identified that the 7T4 and 7T5 cells have best read stability at 314 and 324 mV, respectively. In terms of read time requirement, the 7T4 and 7T5 cells are identified to be the best at  5 ps each.