FIFO Memory Implementation with Reduced Metastability

Clock domain crossing, often known as data interchange between systems operating at different clock frequencies, can occur in a situation involving digital engineering. In modern-day computers, the clock speeds are in terms of GHz and also have very high data rates. The major problem encountered in this system is the data loss. Since different systems operate at different clock speeds, there is a very high probability of data loss depending on the clock speeds. Therefore, it is necessary to prevent these data loss in the computers and the best way of preventing it is with the use of first-in first-out (FIFO). FIFO can be used as a temporary storage which can store the data that is being transferred between two systems in the computers. During the design, the area, cost, and power dissipation are very important constraints of memory. In this designed system, the data loss is significantly reduced as multi-level synchronization techniques are utilized. Due to relatively less processing taking place, speeds of the overall system are significantly increased and the power consumption of the system is considerably reduced. Since many status flags are used, the overflow and underflow conditions are overcome. In this work, design and implementation of synchronous and asynchronous FIFO with a single and a dual clock is carried out to overcome the problem of synchronization and to reduce the metastability that arises while working with the asynchronous inputs of reading and writing and providing stable inputs to the FIFO. The design is simulated using Verilog Hardware Description Language (HDL) and verified on EDA tools using timing analysis.