A Novel D-Latch Design for Low-Power and Improved Immunity

In this paper, different D-Latch designs are proposed at 7 nm technology node using fin field-effect transistor (FinFET) device. FinFET D-Latch circuits are designed using INDEP technique, and the comparative analysis is carried out using the conventional FinFET D-Latch designs. In addition to this transmission gate-based FinFET D-Latches are also designed using ASAP7 PDK at 7 nm technology node. Different performance parameters are analyzed, including average power dissipation, propagation delay, power delay product, and area. The average power dissipation is reduced by 7.7% in FinFET INDEP D-Latch in comparison with the conventional FinFET D-Latch. Moreover, the power delay product is decreased in the case of proposed FinFET INDEP D-Latch in comparison with the conventional design. In the case of transmission gate-based INDEP FinFET D-Latch design average power dissipation is reduced by 14.5% as compared to transmission gate-based FinFET D-Latch. The reliability of FinFET D-Latch is examined using Monte Carlo approach for 10,000 runs, which clearly demonstrates the superior performance of FinFET INDEP D-Latch as compared to conventional FinFET D-Latch circuit.