Design of Configurable Processor Using Custom Instruction with EDK for FPGA-Based Embedded System

Field programmable gate arrays (FPGAs) lie in the area between programmable logic devices (PLDs) and the application-specific integrated circuits (ASICs). They have the property of functionality customization and can be used to implement a complex and large function with millions of logic gates. FPGAs offer massive parallelism to achieve the better performance in the compute-intensive applications like scientific computation, image processing, and digital signal processing (DSP), etc. The closely coupled coprocessor can be used to accelerate the performance in case of compute-intensive applications. The increase in performance can be achieved using the coprocessor by off-loading the processor pipeline. In case of Virtex-4 FPGA using the PowerPC 405, these coprocessing functions can be called either by using the pre-defined instructions or with user-defined instructions (UDIs). These instructions can be used in autonomous or non-autonomous mode. The auxiliary processor unit (APU) controller in the PowerPC 405 fabric core supports up to eight UDIs to make whether to set the condition register or not. The UDIs are decoded by the APU controller and executed by the fabric coprocessor module (FCM). This APU-integrated system improves the overall solution efficiently for various signal processing applications.