Design of Low Phase Noise PLL with Improved Locking Time

In this paper, low phase noise CMOS Phase Locked Loop (PLL) has been designed using a current source voltage-controlled oscillator (VCO), charge pump and Phase Frequency Detector (PFD). The proposed PLL VCO can operate in the band of 600 MHz to 5 GHz. The design has been simulated on cadence virtuoso tool at gpdk 90 nm technology scale with 2 V supply voltage. The phase noise of overall PLL is measured to be 125.53 dBc/Hz whereas the phase noise of VCO is 156.8 dBc/Hz. In addition, the PLL has a locking time of 6 µs due to the utilization of charge pump with dynamic Charge Transfer Switch (CTS).