Design of Low Power 11T SRAM Cell Using CNTFET Technology

With the miniaturization of CMOS technology, the conventional CMOS-based SRAM is facing several challenges, such as increased power consumption, decreased stability, and limited scalability. Carbon nanotube field-effect transistors (CNTFETs) have emerged as a promising alternative to CMOS technology due to their excellent electrical properties, including high electron mobility, low leakage current, and high mechanical strength. This paper presents a low power 11T SRAM cell using CNTFET. The proposed 11T SRAM cell is designed using P-CNTFET as header switch and an N-CNTFET as a footer with separate read circuit and is stimulated using H-Spice tool using 32 nm CNTFET Stanford model. The proposed SRAM cell is operated with the supply voltage of 0.9 V to improve read noise margin of 0.246 V and improved read delay of 0.01627 ns with a write delay of 0.0645 ns. A state of art comparison with existing with CNTFET-based 6T, 7T, 8T and 11T SRAM cells is also presented.