Ferroelectric n-FET Device Physics Based Review

Ferroelectric negative capacitance (NC) FET is the new attractive FET architecture that can be used for today’s gate-all-around (GAA) nanowire and stacked nanosheet, complementary FET architecture with possibility of high drive current (as per roadmap), low Ioff, low subthreshold slope less than 60 mV/decade, and high Ion/Ioff > 106. The biasing of gate voltage effectively in the negative capacitance window or range of S -shaped polarization curve which may be function of ferroelectric dielectric thickness is the key for maintaining a stable subthreshold slope < 60 mV/decade at very low Ioff. So far, properly tuning electric field potential in the internal metal gate of metal-ferroeletric-metal-insulator-semiconductor (MFMIS) is a concern for stabilizing the subthreshold slope as Ioff value is increased to some order from its lowest minimum. High drive current as per roadmap is possible even using simple HfO2 dielectric instead of HZO or Hf 0.5 Zr 0.5 O2 dielectric. The scaling challenges emanate from nonstoichiometry based defects present in the ferroelectric film and the interfacial quality with silicon which makes the subthreshold slope largely and unstably varying over a restricted range of Ioff variation. Atomic layer deposition (ALD) must be used to maintain lower subthreshold slope uniformity over Ioff change by 1–2 order from minimum.