Performance Projections of Negative Capacitance FET for Low-Power Applications

For the past few years, conventional device scaling has been the main design paradigm for MOS devices. This aggressive scaling would ultimately come to an end due to the inability to completely eliminate the heat generated by MOSFET transistors. Power dissipation would be significantly decreased if FETs could run at lower voltages rather than having an excessively high on-current. In that attempt, the lower voltage requirement might be met if the conventional gate oxide were to be replaced with a new stack that provides a usable negative capacitance (NC). When looking into the gate of a MOSFET, a negative capacitor has the ability to raise the total capacitance above that of a traditional MOS device. As a result, less voltage than would otherwise be necessary to produce the same amount of charge in the channel. It is known that ferroelectric materials can produce an effective NC within a certain polarization range.