Device Physics and Modeling Attributes of Tunneling Based MOSFET Device Architectures

Tunnel FET (TFET) is a steep slope ultra low power consumption and switching device that can enable subthreshold slope in the vicinity of 20 mV/decade at T = 300 K. Band-to-band tunneling (BTBT) at the source p+-n+ junction and the structural design of p+-n+ junction and its underlap with gate -dielectric stack determine the tunneling probability and its drive current. Although T-FET provides lower drive current than conventional MOSFETs, its subthreshold or off current is much lower making Ion/Ioff ratio high. In this chapter, various structures of tunnel FET architectures are reviewed from the perspectives of higher on current drive and a methodology is described to extract tunneling mass which determines the tunneling probability rate at the source junction and ultimately enhancement of drain current in TFET architectures.