Moore’s Law Based Scaling Challenges and Their Device Physics Based Reviews

Key issues related to scaling of ultrascaled MOSFETs are identified and some of their device parameter adjustments and other solution enabling procedures are discussed and reviewed in this chapter like complexities arising from ultrashallow junction formation at source and drain of a miniature FET, ion implantation technology, and their variant like single ion implantation technique for precise positioning of dopants in the substrate close to channel, ways to reduce gate tunneling leakage current, and source to drain direct tunneling leakage current, degeneracy related modeling issues mainly affecting DOS effective masses of electron and hole in silicon at T = 300 K and also conductivity effective masses at high doping where experimental calibrated values are rarely found or attempted. Advanced deposition techniques like atomic layer deposition (ALD) and atomic layer etching (ALE) are referenced in this chapter for future precision nm thick any layer and metal deposition and etching. Focus was made on scaling length reduction for 3D, 2D, and 1D FET structures for better gate to channel integrity and short channel effects immunity.