High-NA EUV: Prospects and Challenges and Stochastic Defects Related Manufacturing Yield Loss

High-NA EUV lithography deemed as the most successful patterning technique for feature sizes as low as 2–3 nm for FET architectures is reviewed for its patterning efficiency and associated bottlenecks that introduce various forms of stochastic defects causing high percentage of yield loss at wafer line test or burn-in test. Secondary electrons related stochastic defects such as resist blur, photon shot noise, LER, and LWR are identified as possible defects detected for yield-related failures. A possible technique to minimize the concentration of secondary electrons near the resist top surface is proposed for the first time by the author in this chapter. Curbing or minimizing the secondary electrons concentration is identified as the most unresolved issue today from the perspective of making high-NA EUV lithography a successful technique the semiconductor industries are looking for deployment.