Advanced Lithographic Techniques for Sub-nm Lithographic Resolution of Feature Length

Potential lithographic techniques that are applicable to 2–3 nm various forms of device architecture manufacturing for logic and memory devices are discussed in this chapter with the author’s explicit suggestion over the main prospective lithographic techniques alternative to high-NA EUV lithography, which is currently intensely pursued, and is presented with reasoned and practical expectations from manufacturing yield perspectives. The application areas of various lithographic techniques are also pointed out from the literature.