Development of Low Power and Area Efficient Multi-core Memory Controller Using AXI4-Lite Interface Protocol

In multi-core SoC systems, memory latency is turning out to be a crucial bottleneck in recent times. The overall performance of the system depends on the latency present in both the memories namely on-chip memory and off-chip memory. These latencies occur during the memory read and write operations. In conventional multi-core SoCs, individual memory controllers were employed to execute the read and write operations in on-chip and off-chip memories. This paper proposes an integrated memory controller for multi-core SoC using Advanced Extensible Interface (AXI4Lite) protocol. The proposed model improves the overall speed of the multi-core SoC by utilizing the burst mode capabilities existing in the AXI protocol. The proposed architecture is implemented in System Verilog HDL using Vivado tool. The experimental results prove that the proposed approach exhibits better results in terms of power consumption and area compared to the conventional approaches reported in the literature. The numerical metrics presented show a significance power reduction of 90% by using the proposed model.