Design and Analysis Delay of FinFET and CMOS 6T SRAM Using 22 nm Technology

Now-a-days, in the digital technology era, Static Random Access Memory (SRAM) plays an important role to provide memory capacity for electronic devices. FinFET has claimed many challenges and problems related through the modifying of traditional CMOS transistor devices. Because of its many leading characteristic, particularly in the zone of low voltage, low power, and higher speed for SRAM cell, in this way FinFETs are replacing CMOS (conventional) circuit as the superior choice. By the designing of Static RAM (SRAM) cell which is motivation to reduce delay and increase its performance. Hence, it is providing to be a favorable alternate to solve difficulties because of its undersized area in between source and drain region played in MOSFETs (conventional) semiconductor. In this paper, we have studied and obtained the performance of FinFET-based 6T SRAM cell circuits applied and these FinFET cell’s work functions are paralleled to CMOS (conventional) transistors by the way of propagation delay and operation sustained in Static RAM. In other ways, the estimation of traditional 6T SRAM cell crosstalk line voltage, values are retained for both bit lines wire (BLs), word line wire (WL), and outputs are analyzed according to the circuits. In this way by using right nanometer technology of the semiconductor transistor these values can be achieved and managed. In the industry, it is very important for the SRAM cell to have minimum propagation delay. Thus, the delay of proposed 6T Static RAM circuit has been designed and calculated.