RERL Circuits Design Using Adiabatic Technique

In digital electronics circuits with irreversible logic operations, erasing of each bit results in a heat dissipation of kT ln 2 J. It is possible to lower dynamic power, which is a primary source of energy dissipation using reversible styles. This can be achieved by making use of adiabatic switching principles. The adiabatic approach can be utilized in CMOS circuits to minimize energy dissipation. It can be utilized to recycle the energy that has been stored at the load capacitor. The energy that has been stored can be recycled back into the power source rather than being released as heat. Adiabatic switching technique can be employed by adiabatic logic families like fully adiabatic and quasi-static adiabatic logic. RERL which uses reversible logic to eliminate non-adiabatic losses belongs to fully adiabatic logic family. In this paper, RERL mux design using eight-phase clock and RERL AND/NAND gate and RERL NOT/BUFFER gate using four-phase clock are proposed. At low speed operation, the energy consumption by all these circuits is less. The power dissipation of RERL circuits is less, according to simulation studies using HSPICE.