An Insight into Algorithms and Self Repair Mechanism for Embedded Memories Testing

This paper covers the critical review of algorithms related to Memory built-in self-test and repair based on key parameters including area overhead for spare register, memory row/column size, local bits, main memory sizes, testing time penalties, and repair rate. This paper reviews the concept of memories testing BIST and built-in self-memory repair BISR using different RA algorithms in brief. In MBIST March C, March C- and March LR are simulated for different Memory sizes. March LR shows better fault coverage and requires less testing time. For MBISR different repair redundancy algorithms are simulated for various cases of Spare row/column size. CRESTA shows the optimal repair rate as compared to other repair algorithms. In this paper, we have simulated the co-design of MBIST and MBISR March C, March C-, and March LR as base testing algorithms for MBIST and MBISR ESP with a spare row/column of one row and one column with a memory size of 6*6*1. With this implementation, we found that March LR requires less testing time and co-designing of hardware reduces the hardware penalty.