Design and Verification of 3D Network-on-Chip Router

Devices with rapid speed, low power, and minimal space usage are necessary for modern life. An increase in the amount of data transfer from one IP block to another existing on the same chip reduces the operating frequency of the system-on-chip device due to an increase in the number of IP blocks. Network-on-chip router can operate at a higher speed and consume less area, which is a viable solution to the stated problem. Furthermore, the performance of the network on chip router can be significantly improved by adding 3D IC technology, which improves network throughput and provides minimal latency. The 3D NOC router has been designed by reversible logic to prevent loss of information and to reduce heat dissipation, gate counts, and garbage outputs. In the paper, 3D NOC router has been designed and verified using Verilog HDL. An improved reversible logic-based 3D NOC router has been simulated and synthesized. The results indicate low latency, high performance, and improved frequency design.