FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL

A true random number generator (TRNG) based on a linear feedback shift register (LFSR) and an all-digital phase-locked loop (ADPLL) is a type of hardware-based random number generator that uses the principles of both LFSR and an ADPLL to generate random numbers. We extend an approach that uses on-chip jitter and metastability state in this study. 15-bit LFSR with ADPLL-based TRNG (15-LAT) architecture is created with the help of ring oscillators, flip-flops, ADPLL, 15-bit LFSR, and other physical devices that generate various sources of entropy. When compared to other existing TRNG designs, we established that our novel design lower the complexity as well as decreased the power usage (0.072W) due to the use of minimum FPGA hardware resources. This architecture offers better performance over conventional TRNGs and opens up possibilities to design a more efficient, low-power producing highly reliable TRNG. The architecture was tested on an Artrix-7 FPGAs evaluation board with positive results. A digital storage oscilloscope (DSO) is used to record the resulting pattern and FFT pattern of the corresponding wave. We provide the results of statistical analyses performed on the output bit sequence generated by our design using the MATLAB tool. The NIST SP 800-22 assessment demonstrates that the output TRNG bitstreams are unpredictable and stochastic, suggesting that the suggested architecture is better suited for cryptographic applications.