Design of a Sensitivity-Improved On-Chip Temperature Sensor Based on Inverse-Widlar Architecture

In this paper, a sensitivity-improved on-chip temperature sensor is designed and demonstrated for heavy workload and fast processors. The temperature sensor is based on a self-stabilized inverse-Widlar architecture, which utilizes the concept that in a small temperature zone, threshold voltage varies linearly with temperature. The circuit was designed, simulated, and validated using Cadence in SCL 180 nm CMOS technology. The designed temperature sensor exhibits higher sensitivity of 1.81 mV/ °C and integral nonlinearity (INL) of ± 1 °C in the temperature range of -20 °C to 100 °C. Also the higher sensitivity of sensors will utilize lower bit ADC for operation, saving on-chip area and can be used efficiently for thermal guardbanding in fast processors.