Design and Realization of Logic Gates Using Double Gate Tunnel FET

Tunnel FETs in digital applications may replace MOSFETs because TFET offers distinguishing properties that make them suitable for digital applications, despite TFETs having a low ON-state current and slower speed than CMOS. In the proposed work, silicon-based DG-tunnel FETs for Boolean operations (AND, OR, NAND, and NOR gates) are explored. Each gate is individually biased for this purpose. Silicon body thickness and overlapping of gate-source are crucial features in the implementation of logic gates. The ON-state current of the Si-based TFET is low; therefore, the first Si-Ge-based TFET is also investigated for OR gate functionality. Compared to Si-based TFET, employing Si0.5Ge0.5-based TFET results in one order of magnitude rise in ON-state current. Atlas version of 5.0.10.R is utilized to generate simulation results. The simulation outcomes clearly illustrate that each AND, OR, NAND, and NOR gates may be realized on a single device.