Design-Space Exploration of Conventional/Non-conventional Techniques for XOR/XNOR Cell

This paper provides an in-depth analysis of the different conventional and non-conventional design methods utilized for XOR/XNOR cells, which serve as the fundamental circuit for many high computational arithmetic logic circuits in low-voltage low-power VLSI designs. The ultimate goal of any researcher is to optimize the circuit performance in order to decrease the power consumption of the circuit while maintaining minimum area requirement and higher speed. In this work, challenges of conventional and non-conventional design methodologies have been discussed. A comparative analysis of various XOR/XNOR cells that are available in the literature has also been done. In this research, it is found that if carbon nanotube field effect transistor (CNTFET) technology is used at lower technology node, the circuit’s performance increases in term of speed while floating gate metal oxide semiconductor (FGMOS) technology shows better performance in term of power consumption. FinFET technology is also discussed in this treatise. Unavailability of appropriate simulation model and the complex fabrication process are the major challenges for the non-conventional technologies.