Design of High-Speed SRAM Cell Using FinFET Technology

In today’s scenario, we can notice that memory takes up more than 85% of the available chip space. For all integrated devices from computers to various handheld devices, there is high requirement of faster and low power-consuming memory systems. Till today, all the memory devices such as SRAM and DRAM are mostly using the traditional MOSFETs. As the MOSFET-based memory devices provides the required performance but to further shrink the size of the transistor and to get better power-related outcomes and delay, we have a novel design called FinFET. In order to reduce the short channel effects and to get the acceptable gate control over the channel, FinFET technology can be the better option. In this paper, the design of conventional 6T SRAM cell is done using both MOSFET at 45 nm and FinFET at 14 nm technology nodes in Symica DE tool. The comparison of those designs is made in terms of power consumption and delay parameters. The simulation results demonstrate that FinFET-based SRAM cell offers better performance with less power consumption and delay. Along with the conventional design, SRAM cell is designed under sleep transistor, forced stack, DTMOS, and VTMOS techniques individually and with combinations like DTMOS–sleep transistor, DTMOS–forced stack, VTMOS–sleep transistor, and VTMOS–forced stack with FinFET technology. The simulation results indicate that the sleep-transistor-driven SRAM cell yields best performance in terms of power consumption. Furthermore, the DTMOS using sleep-transistor-based SRAM cell provides less delay compared to other designing techniques.