Design and Implementation of an Optimized High-Speed Vedic-Based Squarer Circuit Using Reversible Logic Gates

The primary purpose of this research is to investigate and evaluate the effectiveness of a 4 × 4 squarer circuit based on Vedic mathematics and reversible logic gates. A high-speed squarer circuit has been developed using Fredkin, Peres, BME, and HNG gates. The simulations are performed using the iSim simulator in Xilinx ISE 14.7. In addition, using several FPGA models, the delay, a fundamental aspect of a digital circuit, is also explored. The individual blocks of the existing circuits are implemented using different types of available reversible logic gates. Lastly, a comparison of the proposed circuit's different attributes with those of the existing designs such as gate count, the proportion of ancilla inputs, and garbage outputs and quantum cost are calculated and presented in a tabular form. Along with this, a brief comparison of FPGA hardware utilized and power consumed is also given. Finally, it is noted that as the quantum cost is greatly decreased by around 75%, also the delay is improved compared to the existing designs by 2.7%, and hence the proposed circuit becomes a viable candidate for high-speed applications.