Design and Implementation of Bus Ticketing System Using Verilog HDL

Buses are the backbone of public transportation in urban India. The existing physical ticketing process is slow, unreliable, and inconvenient. This paper introduced a ticketing system that allows a seamless ticketing experience for the passenger. Passengers will be able to choose their desired destination and ticket count. We introduced a feature where students and senior citizens can claim their rebates as per the government-set reimbursement on bus fares. The module has been designed and synthesized with Xilinx Vivado ISE using Verilog Hardware Description Language (HDL). The ticket generation, coin, and change processing section uses Moore finite state machine (FSM), which allows simplicity in the designing process. A total power consumption of 27.34 mW and 6.134 ns delay at a maximum clock frequency of 130 MHz has been estimated for the proposed design. The RTL schematic and process simulation of the functional system has shown in this paper. The simulation has been carried out using ISim wave-view software.