Implementation of Energy Efficient Full Adder for Arithmetic Application

This study reports the implementation of a hybrid CMOS-based 1-bit full adder (FA) circuit. The need for noise robustness, better drivability and low-energy operation for deep submicron encourage the examination of the hybrid design style. Hybrid CMOS design techniques are utilized to propose new full-featured adders with the desired performance. Module I (XOR-XNOR) generates the XOR-XNOR output simultaneously. Module II and Module III are implemented using the PTL and TG logic. In this work, 16 nm FinFET technology is used to implement a novel design of hybrid FA. The proposed design shows 29.37–71.90% and 38.96–81.56% improvement in power consumption and PDP, respectively.