Resource-Efficient TCAM Implementation Using SRAM

Although ternary content-addressable memories (TCAMs) are faster in operation than static random access memories (SRAMs), TCAMs have disadvantages like high power consumption, low bit density, high cost, and complex circuitry. This paper presents a novel approach to adding SRAM advantages to TCAMs using the technique of hybrid partitioning. In hybrid partitioning, the TCAM table is divided both horizontally and vertically. These partitioned blocks are directly mapped to their corresponding SRAM cells. To justify the functionality and performance of the design, a 64 × 32 SRAM-based efficient TCAM is successfully designed on Xilinx Field-Programmable Gate Array (FPGA) using Verilog HDL. Design parameters were improved in all corners like speed by 10.52%, power by 7.62%, and resource utilization by 50% compared to the best performance reported in literature. And also application-specific integrated circuit (ASIC) of the architecture is designed on the 45-nm CMOS technology node to check the feasibility of design on the chip, and similar to FPGA-based architecture, ASIC implementation performance is also improved.