Through Silicon Vias for 3D Integration—A Mini Review

Three-dimensional integration of integrated circuits (ICs) has shown a better utilization of space on the substrate by stacking the chips one onto another than its planar counterparts. This effective use of space and thus miniaturization has led to a holistic performance enhancement of the very large-scale integration (VLSI) systems. Vertical interconnects or through silicon vias (TSVs) are the foundation of 3D integration. The fabrication technologies required to incorporate the through silicon vias in the substrate and the challenges associated with their fabrication are significantly important, as these may hugely affect the final product performance and cost. To increase the reliability and maintain the signal integrity of an overall IC, various novel structures of TSVs have been devised by the researchers, wherein it is attempted to find the better geometry, shape, and filler materials for the vias. Subsequently, a brief overview of the different aspects of TSVs for 3D integration is presented in the current chapter. The electrical characteristics of the vias are highlighted, considering the lumped equivalent model which may be analyzed using various numerical techniques.