Explicit Power-Delay Models for On-Chip Copper and SWCNT Bundle Interconnects

In the present chapter, the transient behavior and delay investigation of high-performance interconnects is modeled using finite-difference time-domain (FDTD) technique. Further, an explicit power estimation model for both on-chip conventional copper and futuristic single-wall carbon nanotube (SWCNT) bundle interconnects using FDTD technique is proposed. The model deals with the analysis of two signaling schemes, namely, voltage-mode signaling (VMS) and current-mode signaling (CMS). Power-dissipation, delay, and power_delay_product are the interconnect performance metrics considered. The interconnect is characterized by equivalent single conductor model and CMOS inverter gate is used to drive it. It is investigated that CMS scheme is good for delay-centric designs while for power-centric designs, VMS scheme can be adopted. However, owing to lower power_delay_product, CMS outperforms VMS scheme. Further, it is analyzed that SWCNT bundle interconnects are better in terms of energy efficiency as compared to copper interconnects. The results of the proposed analytical model are validated using SPICE, with a maximum error of less than 3%.