Delay and Overshoot Modelling of Asymmetric T-Tree Interconnects

With lower technology nodes and higher data rates, signal integrity has become a big challenge nowadays. The chip performance and signal integrity depend on interconnect delay in deep submicron (DSM) technology nodes. The performance and packing density of high functionality chips are limited by the interconnect delay than the overall circuit delay. This paper discusses the delay and overshoot modeling of asymmetric T-tree interconnect. These delay and overshoot modeling are performed based on the numerical Laplace inversion method. The proposed model is based on the Gaver-Stehfest method, which provides a relationship between the time-varying function and the linear combination of values of transform function. In this work, 50% delay and overshoot are estimated for asymmetric T-tree interconnect for different line lengths, source resistance, and load capacitance. In order to validate the accuracy of the proposed model, the estimated 50% delay and overshoot values are compared with the standard LT Spice model and are found to be in good agreement.