Design and Verification of AMBA AHB Protocol Using UVM

SOC's have multiple blocks integrated on a single chip, to interact between these blocks, on-chip bus architecture is required. ARM's AMBA (Advanced Microcontroller Bus Architecture) is one of the extensively used on-chip architecture used in the VLSI industry. AHB (Advanced High-Performance Bus) is an AMBA Bus protocol with high-performance, supports multiple masters and multiple slaves and has wider bandwidth; as a result of these features, AHB is generally used in SOC's. Previously, AHB design was verified using either Verilog or system Verilog, where the time spent on verification was more than the time spent on design. A more effective verification methodology, like UVM (Universal Verification Methodology), must be adopted to reduce the average time spent in verification and increase efficiency. An AHB protocol with one master and three slaves is designed in ModelSim using Verilog and verified in QuestaSim using UVM, and a coverage report is generated. QuestaSim and ModelSim are the EDA tools developed by Mentor Graphics for design and verification purposes.