Approximate Compressors-Based Multiplier for Image Processing and Neuromorphic Modeling

Approximate computing in the era of high-speed multimedia applications increase in the demand of high-speed error-tolerant circuits. In this method, accuracy is compromised to achieve high performance. The main criterion is to reduce hardware complexity, power dissipation, and timing delay at the cost of accuracy. The main aim of this paper is to design and analyze two approximate compressors with minimum hardware complexity, delay, and power with reasonable accuracy, when compared with the existing compressors in literature. The proposed designs are implemented and verified using 90 nm Cadence NC-Verilog standard library cells. The parameters of interest in the approximate computing are Error Rate (ER), Error Distance (ED), and Accurate Output Count (AOC). The proposed compressors are used to implement 8 × 8, 16 × 16 unsigned multipliers, and signed 8 × 8 approximate multipliers. The application of the proposed design in image smoothing, multiplication, and LIF neuron modeling is discussed.