Classification of IC Products by Manufacturing Processes

The invention of the first IC by Jack Kilby in 1958 led to the bipolar junction transistor (BJT) process, while the first planar IC process conceived by Robert Noyce in 1959 evolved into planar CMOS process by C. T. Sah and Frank Wanless in 1963. The planar CMOS process has been the most widely used process to date for IC designs from the early technology node of 10 um in 1971. The combination of BJT and CMOS processes has also brought in several new technologies, such as double-diffused metal oxide semiconductor (DMOS), bipolar CMOS (BiCMOS), and Bipolar-CMOS-DMOS (BCD) processes. In 1998, the FinFET technology, a “3-D transistor” or a non-planar process, had been demonstrated at UC Berkeley. Meanwhile, the SOI technology, being immune to the latch-up issue, was developed to meet radiation-resistant requirement in space applications. These IC technologies together with several technologies based on III-V compound semiconductor materials, including gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), and others, are discussed in this chapter.